PsiQuantum and AMD Expand the Computing Behind a Quantum Machine
The expanded partnership covers processors, graphics accelerators and software, alongside research on a decoder designed to keep pace with quantum errors.
Published November 13, 2026Intelligence / Frontier Tech / Experimental Systems
PsiQuantum and AMD plan to build more of the conventional computing infrastructure that a large quantum computer will need. Their expanded partnership, announced November 12, brings processors, graphics accelerators and software into a collaboration that already included programmable chips.
A quantum calculation depends on surrounding electronics to handle data and help keep errors under control. The partners will co-design that infrastructure and explore applications combining photonic quantum computing, conventional high-performance computing and artificial intelligence. AMD also plans an equity investment in PsiQuantum.
The companies identify drug discovery as an initial application focus. Their announcement describes computing methods and simulations already running on AMD hardware, alongside work intended for future fault-tolerant quantum machines. It provides no independent benchmark establishing the broader performance claims.
One specific piece of the collaboration is described in a research preprint submitted November 10 by PsiQuantum and AMD researchers: a machine-learning decoder called PRISM.
Keeping up with errors
In photonic quantum computing, photons carry quantum information. Lost photons leave gaps at known locations. A decoder interprets error signals to help protect a calculation. Its decisions must arrive quickly enough for the larger system to use them.
In simulations of several families of error-correcting codes, PRISM matched a reference decoder's rate of logical errors, meaning failures that remain after correction. The reference decoder uses integer programming, a mathematical optimization method. The results combine simulations and hardware-design work; integration with a quantum computer remains ahead.
For an optimized version mapped to an AMD Versal VP1902 programmable chip at 250 megahertz, the researchers report 10.11 microseconds of decoding latency for the tested blocks. The design's sustained processing rate is equivalent to one block every 2.39 microseconds. Latency measures the time to finish one block; the second figure describes the sustained processing interval.
The paper also reports 6.59-microsecond latency at 400 megahertz, derived from separately mapped network layers. Mapping the full network at that frequency is left to future work.
Primary sources