JetsonsAge

Explore the frontier.

Search published reporting, intelligence and briefs.

Explore JetsonsAge

Quantum computers need help keeping up with their own errors

IBM, AMD and Oak Ridge have opened a shared testbed to study the fast exchange between fragile quantum processors and the conventional computers that help protect them.

Published November 8, 2026Analysis / Frontier Tech / Experimental Systems

A quantum computer can make a mistake while performing a calculation, while checking for mistakes, or simply while waiting. Keeping a long calculation intact requires a continuing exchange of information: quantum hardware reports signs of trouble, and a conventional computer works out how to account for it. The speed and accuracy of that exchange will help determine how much useful work the machine can do.

IBM, AMD and Oak Ridge National Laboratory announced a new place to study that problem on November 5. At IBM’s Poughkeepsie, New York, site, the partners have brought IBM quantum processors together with Oak Ridge’s Umbra high-performance computer, powered by AMD processors and graphics accelerators.

Their immediate objective is practical: give researchers a shared environment in which to test error-correction methods, the computers that run them and the connections between the two. Placing the equipment together reduces communication delays and lets teams investigate the whole process under more realistic conditions.

The launch establishes research infrastructure. Its value will emerge through experiments showing which arrangements preserve quantum information reliably, handle growing streams of measurements and support longer calculations. Those are essential steps toward using quantum computers for demanding problems in chemistry and materials science.

Checking the information without reading it

Quantum information is unusually difficult to protect. Reading out an unknown quantum state generally changes it. Researchers therefore encode information across groups of physical qubits, the individual devices in a quantum processor, and measure carefully chosen relationships among them. These checks reveal clues about errors while preserving the information being protected.

The protected unit is called a logical qubit. The check results form an error syndrome, rather like a pattern of warning lights. A conventional program called a decoder interprets that pattern and the history of earlier checks to infer a likely correction. Because the checks can also be faulty, the decoder has to distinguish a problem in the stored information from a misleading measurement.

Often the result is recorded in a classical bookkeeping system that changes how subsequent operations or measurements are interpreted. Physically reversing every suspected error would add operations and opportunities for further mistakes. Error correction is thus a coordinated activity spanning quantum devices, measurement electronics and ordinary computing.

Two different measures of speed

The decoder faces two timing demands. First comes throughput: it must process checks at least as quickly as they arrive over time. If the incoming stream outruns it, unfinished work accumulates. A quantum program that needs the decoded result before choosing its next operation can then face an increasingly long wait.

The second demand is response time, or latency. A decoder can keep up with a stream by processing several pieces of work at once, yet still take a measurable time to finish each decision. That delay matters whenever the next quantum operation depends on the answer. Communication and control electronics add their own delays to the calculation.

Google’s Willow experiments illustrate the distinction. In work published online in Nature in December 2024, its researchers reported an error-correction cycle lasting 1.1 microseconds and an average decoder latency of 63 microseconds for one tested code. The decoder kept pace through experiments reaching a million cycles. Its processing overlapped with the continuing stream. The reported latency excluded some additional communication and feedback work, and feedback had yet to be implemented in that experiment.

A separate Riverlane–Rigetti collaboration measured more of the full response. Its eight-qubit experiment, published in Nature Communications in June 2026, reported 9.6 microseconds after nine rounds of measurements: 6.5 microseconds for decoding and 3.1 for communication and control. The system used the decoded result to trigger a subsequent physical operation.

The experiments used different codes, hardware and timing definitions. Together, they show why a useful benchmark must identify both how quickly measurements can be processed and how long the complete feedback path takes.

Finding the right division of work

The new platform includes IBM’s 120-qubit Nighthawk processor and Umbra’s AMD Instinct MI355X graphics processors and fifth-generation EPYC CPUs. IBM’s control interface allows researchers to measure during a calculation, respond to results and adjust the timing of control signals. These capabilities let teams examine how their software behaves alongside the hardware it is meant to protect.

“Today, the question is how to accelerate and optimize error correction to build systems that scientists can use to tackle meaningful problems,” IBM Research director Jay Gambetta said in the announcement.

Different jobs may favor different classical hardware. Graphics processors can help researchers train and evaluate decoders and explore methods at scale. Programmable chips called FPGAs can implement tightly timed decoding operations directly in reconfigurable circuitry. The useful division of labor depends on the code, the data movement and the speed required.

IBM’s earlier Relay-BP work shows how much can depend on the algorithm itself. It modifies a message-passing method in which many small calculations exchange estimates about likely errors. Varying how those calculations retain earlier information helps the method escape patterns that would otherwise leave it uncertain or oscillating between answers.

“I took all the cheap bits and tried to amalgamate them together,” lead researcher Tristan Müller said in IBM’s August 2025 account of the algorithm’s development. Here, cheap meant computationally inexpensive: improvements that could strengthen decoding without demanding cumbersome calculations.

An October 2025 preprint then described a Relay-BP hardware prototype on an AMD FPGA. Its iterations took 24 nanoseconds, supporting an average decoding time below one microsecond per cycle under the paper’s specified noise assumptions. Verification used synthetic error-check data. The prototype also occupied more than half the chip’s lookup tables, small programmable units used to build its logic, illustrating how speed, accuracy and hardware requirements have to be evaluated together.

What would make the testbed successful?

A convincing result would connect those engineering measurements to better protected computation. Researchers need to report the logical error rate, how it changes as protection is increased, the number of physical qubits required and the classical resources consumed. Timing measurements should include unusually slow decisions as well as averages, because a program can stall while waiting for a difficult case.

The way unsuccessful runs are handled also matters. One IBM-linked sampling study used error checks to discard suspect runs and improve the quality of the retained results. Such post-selection can establish valuable experimental capabilities. Its cost includes the runs thrown away. Sustained fault-tolerant computation places further demands on correcting errors while useful operations continue.

The Department of Energy’s Quantum Genesis Q Competition sets a broader ambition: systems with at least 100 logical qubits capable of hundreds of millions of fault-tolerant operations and scientific demonstrations. Its accompanying validation initiative calls for checks across hardware, logical architectures, applications and classical control systems. These requirements make reliability a property of the complete machine.

That is where the Poughkeepsie testbed could make its most useful contribution. Researchers will be able to discover which combinations of quantum hardware, decoding software and conventional computing keep working as the workload grows. Each reduction in error, waiting time or resource demand brings a longer, more useful calculation within reach.

Sources

1. IBM announcement: Oak Ridge National Lab, IBM, and AMD Launch New Co-Design Platform for Quantum Error Correction, November 5, 2026.

2. IBM Quantum: ORNL, IBM, and AMD launch co-design platform for quantum error correction, November 5, 2026. Location, workflow and hardware roles.

3. IBM Quantum Learning: Error correction II. Logical qubits, decoding and classical tracking of corrections.

4. Google Quantum AI and Collaborators: Quantum error correction below the surface code threshold. Nature, published online December 9, 2024; journal volume 638 (2025).

5. Caune and colleagues: Demonstrating real-time and low-latency quantum error correction with superconducting qubits. Nature Communications, June 1, 2026. Open manuscript also available as arXiv:2410.05202.

6. Müller and colleagues: Improved belief propagation is sufficient for real-time decoding of quantum memory. Preprint, June 2025, revised August 2025.

7. IBM Quantum: Relay-BP: The world’s fastest, most accurate decoder for qLDPC error correction codes, August 4, 2025. Source of Müller quotation.

8. Maurer and colleagues: Real-time decoding of the gross code memory with FPGAs. Preprint, October 24, 2025.

9. Martiel and colleagues: Sampling hard circuits with verifiably high fidelity. Preprint, version 3, September 2, 2026.

10. U.S. Department of Energy: DOE Launches Competition to Accelerate Development of World’s First Fault-Tolerant Quantum Computer, September 17, 2026.

Sources · 2
More analysis